BTECH MTECHPROJECTS

MATLAB FUNDAMENTALS

PHYSICAL MODELING WITH SIMULINK

DSPIC SIMULINK PROGRAMING

TMS320 SIMULINK PROGRAMING

Introduction to PCB Design Using CadSoft EAGLE

Professional Design with CadSoft EAGLE

Essentials of FPGA Design

Course Description

Build an effective FPGA design using synchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the ISE Design Suite to build, synthesize, implement, and download a design.

Who Must Attend

Digital designers who have a working knowledge of digital design (VHDL or Verilog) and who are new to Xilinx FPGA

Prerequisites:  Working HDL knowledge (VHDL or Verilog) Digital design experience

Software Tools :  Xillnx ISE Hardware

Architecture :  3E series FPGAs

Demo board :  Papilio Board

After completing this comprehensive training, you will have the necessary skills to:

Take advantage of the primary 3E series FPGA architecture resources
» Use the Project Manager to start a new project
» Identify the available ISE design flows (project based and non-project batch)
» Identify file sets (HDL, simulation)
» Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
» Synthesize and implement an HDL design
» Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
» Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)
» Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
» Describe and analyze common STA reports
» Identify synchronous design techniques
» Describe how an FPGA is configured

Embedded System-Microchip PIC Microcontroller With MikroC and Proteus